features jedec standard sdr-sdram supported transaction pipeline for maximum utilization of the mem- ory bus 3 request buffers for transaction pipeline supports cas latencies of 1, 2 and 3 4 or 8 beat burst transactions supported supports up to 4 chip selects of memory devices page mode support for up to 16 open pages supports flexible row and column addressing supports up to 4gb of memory address space supports registered dimm mode supports auto refresh and self refresh refresh for populated banks only automatic refresh of idle slots interrupt generation for invalid address requests programmable refresh rate programmable timing parameters configuration register read/ write interface fully complies with standard ocp slave (basic signals) configurable 8/16/32/64-bit ocp slave interface for regis- ter configuration configurable 8/16/32/64-bit memory data bus interface for data transfers functional overview sdr is a very high performance memory controller to interface with sdr-sdram memory devices. it is having three bus interfaces, memory interface, configuration bus interface and host interface. configuration bus and host interface are to communicate with the host. the configuration bus facilitates to program the internal sdr configuration registers. and the host bus is used to ini- tiate the actual memory data transactions. host places the read/write requests on this bus and the sdr core correspondingly performs the data transactions. this bus width is same as the memory data bus width. the typical usage of the core in system is shown in fig 1: V7001 megacell in a typical system. the sdr core is having three internal request buffers which can store three different transaction requests from the host. even though the response to the host is in order with reference to transaction launching, all the transactions in the internal request buffers will be pipe- lined for effective utilization of the sdram memory bus interface. because of processing three requests at same time, the required commands can be launched for all the three requests at appropriate time to achieve the maxi- mum data bandwidth. the sdr supports up to 4 chip selects and each chip select address range is programmable. interrupt can be asserted if the requested address is not falling in any of the chip select address range or when there is an over- lap between two chip select address ranges. the exter- nal interfaces to the core are indicated in fig 2: V7001 megacell i/o diagram memory controller sdr-sdram arbiter proc1 local port controller sram rom flash port-x V7001 fig 1: V7001 megacell in a typical system V7001 sdr-sdram memory controller
performance specifications target applications can be easily interfaced to any soc designs that need to interact with sdr-sdram in embedded memory intensive applications test coverage design is highly synchronous and scan friendly fault coverage is 94% with atpg vectors deliverables fully synthesizable verilog rtl source code documentation - data sheet, user guide, verification description document self checking verification suite synthesis scripts scripts for sta & dft (optional) parameter value remarks gate count ~26 k for 32-bit configuration bus and 32-bit memory bus code coverage 100% block, arc, state transitions, expressions, events openmore score 96% technology 0.18 artisan, tsmc frequency 170 mhz sta verified with pre-route, pre-scan netlist fig 2: V7001 megacell i/o diagram sdcs_n_o[3:0] sdma_o[12:0] sdras_n_o sdq_o configuration registers request buffers sdr_rw sdr_addr sdr_wdata i/f i/f host mem V7001 sdq_i sdqm sdclk_o sdr_be sdr_rdata sdr_wdata_ack sdr_rdata_vld sdr_req_vld sdr_req_ack sys_clk reset_n configuration bus (ocp basic) sdcas_n_o sdwe_n_o sdba_o[1:0] sdq_o_en sdclk_i qcl_10208_df_02_datasheet_rev101 qualcore logic, inc. 1289, anvilwood avenue sunnyvale, ca - 94089, usa tel: 408 541 0730 fax: 408 541 0740 e-mail: sales@qualcorelogic.com http://www.qualcorelogic.com
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